1. Field of the Invention
The embodiments of the invention generally relate to phase adjusting and phase adjusting mixer circuits and, more particularly, to phase adjusting and phase adjusting mixer circuits that incorporate a variable delay device having multiple individually selectable field effect transistors (FETs) for selectively programming delay. The embodiments of the invention further relate to design structures embodied in a machine readable medium for designing and manufacturing such micro-phase adjusting and micro-phase adjusting mixer circuits.
2. Description of the Related Art
With recent advances in semiconductor technology, integration levels have increased to the point where the functional capabilities of a single system-on-a-chip (SOC) produced today may exceed those of an entire computer that was produced less than five years ago. For example, complex analog functions (e.g., physical layer transceivers and high speed serial interfaces) are routinely integrated into such SOCs. Operation of such high speed interfaces commonly requires a means of phase synchronization to correctly sample incoming data. Today, phase synchronization is typically accomplished using a phase rotator designed to mix several phase-related signals to create a selectable phase offset However, while adequate for current clock speeds and de-serialization usage, these phase rotators are large, expensive, complex and have limited frequency/granularity.
Technological advancements have also recently been made allowing for embedded radio frequency (RF) functions within larger digital integrated circuits. These RF functions may see performance benefit if clocks can be more tightly aligned using phase shifters. Furthermore, current logic designs often require delay of clock or data signals in order to correct for timing (setup or hold) violations in various logic paths. However, because analog functions (e.g., phase rotators and delayed locked loops (DLLs)) are expensive to implement, phase adjusting circuits that incorporate fixed delay cells are typically used. Such phase adjusting circuits use a path of delay cells (e.g., inverters) designed to provide a significant fixed (i.e. non-programmable) delay that varies over process, voltage and temperature (PVT) with other logic cells. The delay variation between best case (BC) PVT and worst case (WC) PVT may be more than 2 times. Because of this, a circuit designer must often balance the need for adding delay to a path to correct timing issues at the BC corner with the increase in delay at the WC corner. Therefore, there is a need in the art for a circuit topology which provides for low cost programmable input signal phase-adjustment capability in order to fine tune input signal arrival and data synchronization in digital systems.